Computer Aided Design of fault-tolerant VLSI systems
Computer Aided VLSI synthesis targeting deep sub-micron reliability/low power
High-speed architectures for network protocols and encryption
D. Sonecha, B. Yang, R. Karri, D. A. Mcgrew "High-speed architectures for binary-tree based stream ciphers:Leviathan case study, " Journal of Microprocessors and Microsystems, to appear.
Kaijie Wu, Ramesh Karri, " Fault Secure Datapath Synthesis using Hybrid Time and Hardware Redundancy ", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Oct, 2004, Vol 23, No. 10, pp 1476-1484
Kaijie Wu, Ramesh Karri, " Selectively Breaking Data Dependences to Improve the Utilization of Idle Cycles in Algorithm Level Re-Computing Data Paths ," IEEE Transactions on Reliability, Dec. 2003, Vol 52 , No. 4, pp 501 - 511
Ramesh Karri, Piyush Mishra, "Optimizing the energy consumed by secure wireless sessions - Wireless Transport Layer Security case study", Journal of Mobile Networks and Applications (MONET), Kluwer Academic Publishers, April 2003, Vol. 8, No. 2, pp. 177-185.
Kaijie Wu, Ramesh Karri, Piyush Mishra, "Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit RC6 Block Cipher, " Special Issue on Defect and Fault Tolerance in VLSI Systems. Microelectronics Journal, January 2003, Vol 34, No. 1, pp 31-39
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim, "Concurrent Error Detection Schemes for Fault Based Side-Channel Cryptanalysis of Symmetric Block Ciphers, "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. December 2002, Vol 21. No. 12, pp 1509-1517
Ramesh Karri, Kaijie Wu, " Algorithm Level Re-Computing using Implementation Diversity: A Register Transfer Level Concurrent Error Detection Technique, " IEEE Transactions on Very Large Scale Integration (VLSI) Systems. December 2002, Vol 10. No. 6, pp 864 -875.
Kaijie Wu, R. Karri, " Algorithm Level Recomputing Using Allocation Diversity: A Register Transfer Level Approach To Time Redundancy Based Concurrent Error Detection, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 2002, Vol 21. No. 9, pp 1077 -1087
Ramesh Karri and B. Iyer, "Introspection: A Register Transfer Level Technique for Concurrent Error Detection and Diagnosis in Data Dominated Designs," ACM Transactions on Design Automation of Electronic Systems, vol.7, no.1, Jan 2002.
M. Veeraraghavan, Ramesh Karri, T. Moors, M. Karol and R. Grobler, "Architectures and protocols that enable new applications on optical networks," IEEE Communications Magazine, vol. 39, no. 3, Mar 2001.
Ramesh Karri, Kyosun Kim and M. Potkonjak, "Computer Aided Design of Fault Tolerant Application Specific Programmable Processors," IEEE Transactions on Computers, vol 49, no 11, pp. 1272-1284, Nov 2000.
I Hong, M. Potkonjak and Ramesh Karri, "Power optimization using Divide-and-Conquer for Minimization of the Number of Operations," ACM Transactions on Design Automation of Electronic Systems, vol 6, no. 4, Oct 1999.
N. Mukherjee, T. Chakraborty and Ramesh Karri, "Built-In Self Test: A Complete Test Solution for Communication Systems," IEEE Communications Magazine, vol. 37, no. 6, pp. 72-78, Jun 1999.
N. Mukherjee and Ramesh Karri, "An Integrated approach to On-Line/Off-Line BIST," Journal of Electronic Testing and Testability Analysis, pp. 189-200, Dec 1998.
A. Dasgupta and Ramesh Karri, "High-Reliability Low-Energy Microarchitecture Synthesis," IEEE Transactions on CAD, vol. 17, no. 12, pp. 1273-1280, Dec 1998.
Ramesh Karri, Karen Hogstedt and A. Orailoglu, "Computer Aided Design of Fault Tolerant VLSI Systems," IEEE Design & Test of Computers, vol. 13, no.3, pp. 88-96, Fall 1996.
Ramesh Karri and A. Orailoglu, "Time constrained scheduling during high level synthesis of Fault-Secure VLSI Digital Signal Processors," IEEE Transactions on Reliability, vol. 45, no.3, pp. 404-412, Sep 1996.
A. Orailoglu and Ramesh Karri, "Automatic Synthesis of Self-Recovering VLSI Systems," IEEE Transactions on Computers, vol.45, no.2, pp. 131-142, Feb 1996.
A. Dasgupta and Ramesh Karri, "Optimal Algorithms for Synthesis of Reliable Application Specific Heterogeneous Multiprocessors," IEEE Transactions on Reliability, vol. 44, no. 4, pp. 603-613, Dec 1995.
A. Orailoglu and Ramesh Karri, "Coactive Scheduling and Checkpoint Determination during High Level Synthesis of Self-Recovering Microarchitectures," IEEE Transactions on VLSI Systems, vol 2, no. 3, pp. 304-311, Sep 1994.
A. Orailoglu and Ramesh Karri, "Defect Tolerant Layout Synthesis," International Journal of Electronics, pp. 1121-1133, Jun 1994.
A. Orailoglu and Ramesh Karri, "Synthesis of Fault-Tolerant and Real Time Micro architectures," Journal of Systems and Software, pp. 73-84, May 1994.
Ramesh Karri and Alex Orailoglu, "Standard seven segment display for Burmese Numerals," IEEE Transactions on Consumer Electronics, vol. 36, no. 4, pp. 959-961, Nov 1990.
Andhra University, Visakhapatnam, India, Class of 1985
Electronics and Communication Engineering
Bachelor of Engineering
Polytechnic Institute of New York University
1998-07-01 - present
Taught Computer Engineering courses including VHDL Based Synthesis (EL 590), Introduction to VLSI Design (EL 547), VHDL based behavioral synthesis. Coordinator for MS in Computer Engineering. Advising two Ph.D students and two MS students. Director of CAD Lab (LC 010), VLSI Lab (LC 229) and undergraduate computer engineering labs (LC 018).
University of Massachusetts
Assistant Professor of Electrical and Computer Engineering
1993-09-01 - 1998-07-01
Taught computer engineering courses including CMOS VLSI Design, Computer Aided Design, Fault tolerant computing and computer organization. Advised two Doctoral students.
Lucent Bell Labs Engineering Research Center
Member of Technical Staff
1997-06-01 - 1998-07-01
Initiated the research and development effort in on-line built-in self test of VLSICs;
Built a VHDL Library for on-line concurrent fault detection circuits;
Developed techniques for testing embedded intellectual property cores.
University of California
Teaching Assistant for courses in Digital logic design, VLSI Desi
1989-09-01 - 1993-08-01
University of California
Graduate Research Assistant in the VLSI Laboratory
1990-04-01 - 1993-08-01
Fifth Generation Computing Group, Research and Development Center
1988-05-01 - 1989-06-01
Implemented multiprocessor cache consistency protocols and evaluated their performance and scalability.