Ben Epstein is active in a number of military programs related to information security and nanotechnology. Of note were his contributions to secure information flow in the US Army Future Force Warrior Program. He currently serves as a Senior Advisor to DARPA in areas pertaining to IC security and phased arrays. This effort has included the transitioning of advanced X-ray microscopy for imaging ICs as part of an inspection process against Trojan attacks. Other work of Dr. Epstein includes signals intelligence and communications interception of civilian networks, innovative GPU-based approaches to communications jamming, along with core research in bio-machine interfaces and applications (including novel MEMS approaches to covert information flow via insect swarms).
He holds a BS in Electrical Engineering from the Univ. of Rochester, the MS and PhD Degrees in Bioengineering from the Univ. of PA, and an MBA from the NYU Stern School of Business. He served as a Member of the Technical Staff at RCA Labs (now called Sarnoff Corp.) during eight years where he specialized in microwave circuit design, simulation, and test, followed by executive positions at France Telecom’s North American operations. He is presently Vice President of Special Projects at OpCoast LLC, serves as an Associate Research Professor at NYU-Polytechnic University, as well as Chief Strategy Officer for Aqsacom SA in Europe where he oversees programs deploying telecommunications interception, and co-founder of Septet Systems Inc., a business focused on innovative information processing solutions. More recently he joined the Advisory Board of MedSteer SA, a company focused on automated anesthesia delivery systems.
Saverio Fazzari works for Booz Allen acting as a senior technical advisor to DARPA and other government agencies for numerous programs. Mr. Fazzari has a strong background in all areas of semiconductor design and fabrication, from algorithm development through device implementation. His specialty is advanced circuit design and development strategies with a focus on hardware cyber security issues including trusted design and fabrication. Mr. Fazzari’ s experience includes extensive commercial experience, leading production innovation and development across all facets of the electronic design process. Mr. Saverio Fazzari has over 20 years of experience covering the entire electronic product development flow. He has a BSEE from Johns Hopkins, and MSEE from the University of Pittsburgh. He has published over 14 papers in industry journals and technical conferences.
Kevin Gotze is a security validation team lead at Intel's Security center of Excellence (SeCoE) primarily responsible for evaluating desktop and mobile CPU products for security vulnerabilities. Kevin also actively participates in Intel's Product Security Incident Response Team and Security Architecture Forum. Prior to joining Intel, Kevin worked at IBM in Poughkeepsie, NY as a logic designer for Cryptographic coprocessors and Design for Test logic for IBM Mainframe and Unix systems.
Dr. Ryan Helinski is a member of technical staff at Sandia National Laboratories in Albuquerque, NM. Ryan’s research interests include hardware security, Physical Unclonable Functions (PUFs), red teaming, ASIC design and cyber security. He completed his Ph.D. in Computer Engineering at the University of New Mexico (UNM) in December, 2010. His graduate research work was on a PUF defined by the power grid of an IC (a.k.a. the power grid PUF). Ryan was granted Master’s and Bachelor’s degrees in Computer Engineering by the University of Maryland, Baltimore County (UMBC) in December of 2008 and 2006, respectively.
Dr. Michael Isnardi is a Senior Principal Research Scientist in the Vision Technologies Division of SRI International Sarnoff, where he has worked since 1986. His early work included development of the DIRECTV system and Sarnoff’s Compliance Bitstreams product. Recent work includes development of congestion management, salience-based compression and compressed sensing technologies for video transmission over low-capacity networks. Dr. Isnardi is a member of SMPTE and IEEE, and also serves on the Technical Program Committee for the International Conference on Consumer Electronics.
Dr. Robinson E. Pino is a Senior Scientist at ICF International, Fairfax, VA, advancing the state-of-the-art in cyber security by applying autonomous concepts from computational intelligence and neuromorphic computing for the United States Department of Defense. From 2009 to 2012, he was a Senior Electronics Engineer at the United States Air Force Research Laboratory, Program Manager and Principle Scientist for the computational intelligence and neuromorphic research efforts, and contracting officer representative for the DARPA SyNAPSE and Physical Intelligence programs. In industry, Dr. Pino was with IBM, from 2005 to 2009, as an Advisory Scientist/Engineer enabling advanced CMOS technologies as a Business Analyst within IBM’s Photomask business unit. From 2006 to 2009, Dr. Pino served as Adjunct Professor at the University of Vermont where he taught graduate and undergraduate level electrical engineering courses.
Dr. Pino has published over 40 technical papers and two books, and holds five patents and three pending. Dr. Pino has received numerous awards and professional distinctions including the AFRL Early Career Award in 2012, was named Distinguished Lecturer of IEEE, EDS, in 2010, AFRL Information Directorate Scientist/Engineer of the Year in 2011, named Top 200 Most Influential Hispanics in Technology by HE&IT Magazine in 2011 and IEEE Mohawk Valley Section Engineer of the Year in 2011. Dr. Pino received the Ph.D. and M.S. degrees in Electrical Engineering from Rensselaer Polytechnic Institute, Troy, NY in 2005 and 2003 and B.E. (E.E.) degree with honors (summa cum laude) from the City University of New York, City College, in 2002.
Dr. Youngok Pino is a computer scientist at Information Sciences Institute (ISI) and her research focuses on high assurance computing architectures, trusted computing and hardware design for trust and security. Previously, she was both a program manger and researcher at the Air Force Research Laboratory (AFRL) where she was responsible for the research and development on advanced computing architecture technologies to provide secure computational capabilities to information systems.
Dr. Pino began her professional career at the International Business Machines (IBM), Burlington, VT and was involved in developing and implementing ASICs methodologies in the area of Physical Design, Signal/Power Routing, and Timing optimization and developing compact model analytic stress formulation for IBM’s most advanced 32nm node SOI and bulk CMOS technologies as well as passive compact modeling. She received her PhD in Electrical Engineering from Rensselaer Polytechnic Institute.
Kurt Rosenfeld is an engineer at Google in New York. He works on distributed systems, security, and distributed systems security. He has a background in digital and analog hardware design, network security, multimedia forensics, and hardware security. Prior to joining Google, he completed a PhD in Computer Science at NYU-Poly.
Richard Stern is a Senior Hardware Engineer at Cubic Defense Applications. Cubic Defense Applications is recognized as a world leader in military training systems, electronics, asset tracking, and cyber solutions. His research interestes include FPGA's, Encryption and Hardware Security. His recent work involves using FPGA's in an NSA approved Single Chip Cryptography (SCC) flow, with an integrated security monitor, to complete a Multi-Level Security (MLS) system certified to process and output co-mingled data at multiple classification levels. His previous work was on the Joint Strike Fighter (F35) program at L-3 Communications.
Dr. Chengmo Yang received a B.S. degree in Microelectronics from Peking University, China in 2003, a M.S. and a Ph.D. degree in Computer Engineering from the University of California, San Diego in 2005 and 2010, respectively. She is currently an assistant professor in the Department of Electrical and Computer Engineering at the University of Delaware. Her research interests lie in the broad areas of computer architecture and embedded systems, with a particular focus on the development of reliable, secure and power-efficient multi/many core systems. She has served as Program Committee of a number of conferences, including International Conference on Hardware/Software Co-design and System Synthesis (CODES-ISSS), International Conference on Embedded and Ubiquitous Computing (EUC), as well as Workshop on Design for Reliability (DFR). She also serves reviewer of a number of IEEE and ACM journals.