Embedded Systems Challenge

Open to: high school, undergraduates, and graduate students located in the continental U.S.
 

Register/Registration deadline: Coming soon. Please check back.
Team captain: Jeyavijayan Rajendran

Prizes

Master of Science scholarships for students who attend NYU-Poly:

• 1st place: $5,000
• 2nd place: $3,000
• 3rd place: $3,000

Cash prizes for winners: 

• 1st place: $500
• 2nd place: $250
• 3rd place: $100

Travel Grants

One representative from each finalist team will be given a travel grant up to $500 to present and/or demo their work and to attend the award ceremony.

Rules

• Participation in the qualification phase is required. Finalists also compete in the hardening phase, the attack phase, or both.
• To qualify for this challenge, you must first submit a plan (see below)

Scoring

Competition Score

Each attempted attack involves an attacking team that tries to insert a trojan, and a defending team, who provided the hardened chip that is being attacked.

• For each successful attack, the attacking team gains one point and defending team loses 1 point
• For each unsuccessful attack, the attacking team loses one point and the defending team gains 2 points

Report score

Your report will be read by the judges and evaluated on the basis of clarity, detail, and insight.

2009 Challenge (2010 description coming soon)

The focus of this year's Embedded Systems Challenge is on defending chips against malicious modification during manufacturing.There are three phases to this year's chllange: qualification, hardening, and attack (see below for phase details).

The Scenario: You are a chip designer and you have a new chip called Beta that is almost ready for production. You need to send the design to a factory to have them fabricate your chips. The problem is, you don't fully trust the factory. Maybe they will insert a trojan in your chip. The challenge is to to harden your chip with extra logic that will allow you to detect and/or disable trojans.

2009 Challenge Phases

Phase 1: Submit a plan.

Describe in 2 pages how you can embed extra logic in a design so you can detect malicious modifications during fabrication. Be specific. The 10 most promising proposals will be selected as finalists. The 10 finalists will have a Xilinx FPGA development board shipped to them along with the HDL code sent to them for the hardening and attack phases.

Phase 2: Harden a chip.

We will provide HDL code for Beta, a vulnerable reference design of a crypto system. Beta will resemble the Alpha design from the 2008 CSAW Embedded Systems Challenge with the addition of a JTAG TAP. Harden the design against trojans by adding internal JTAG-accessible probing features so you can detect and/or disable trojans in the chip before it is exposed to sensitive mission data. Submit the following to the ESC:

• hardened HDL code (this will be distributed to all ESC competitors)
• test vectors (these will not be distributed)

Make the minimum set of changes necessary to add your test structures. Do not obfuscate the code. You can assume that the test vectors that you provide will be applied to the chip each time it is powered up.

Phase 3: Attack hardened chips.

Attack as many of the hardened designs from the previous phase as possible by embedding one trojan in their design. That trojan should not be detected by their test structures and should have the malicious function of leaking key or plaintext. For each design that you trojaned, submit the HDL and .bit file. We will load the .bit file onto the FPGA and apply the test vectors supplied by your opponent who hardened the chip. We will verify:

• basic system functionality;
• trojan functionality; and that
• the test vectors produce the same response with your trojans as without your trojans.

If the test vectors produce the same result for your trojaned version as for the untrojaned version, we consider your trojan undetected. We define a successful attack to be one that passes all three checks listed above.