VLSI, Electronics and Power

Power Electronics for Wireless Devices
Analysis of Secondary Networks Having Distributed Generation Systems
Mitigation of Voltage Disturbances Caused by Nonlinear Electrical Massive Loads
Development of a Unit Substation Demand Estimator
Mitigation Techniques to Reduce Inrush Currents of Network Transformers
Secure Built-In-Self-Test (BIST) Architecture
Fault Tolerant Nanoscale Systems
Hybrid CMOS/Nano Circuit Design

Power Electronics for Wireless Devices

Participating Faculty: Dariusz Czarkowski

Motivation: Portable power sources such as batteries, fuel cells, and super capacitors; energy harvesting; and wireless power are candidates for powering wireless devices.  Limited life span of portable sources, low output power and unreliability and low efficiency of energy harvesting methods, and inefficiency of wireless power restrict applications and decrease performance of a wireless device or network.  Optimization of the power consumption characteristics of wireless devices and networks can be achieved at many levels of the system design: efficient power distribution systems, low-power demand architecture, power minimizing network algorithms, power efficient network structures, and power aware functionality specifications and requirements.

Goals: To develop power electronics topologies, control algorithms, and supervisory strategies which will minimize the effects of limited energy supply to portable wireless devices. To explore various schemes of energy harvesting and their applications in wireless devices.

Background: This project focuses on power conversion hardware for wireless devices. It is interconnected with other energy conservation WICAT efforts under the DREAM-IT umbrella. The PI has been also cooperating with ConnectionOne Center at Arizona State University and the body area network team at the University of Virginia.  The efforts have resulted so far in 2 conference publications, one MS thesis, and several student research posters. Experimental verification of the research is under way with an objective of journal paper submissions.

Work Plan: Topologies of dc-dc switching converters and hybrid converters will be adapted to the needs of wireless equipment. New topologies will be developed. The work will include simulations of converters with Spice software, layout and its verification with Cadence analog suite, and manufacturing of the prototypes and experimental confirmation. It is expected that the power switching frequencies will reach the range of 100 MHz in order to decrease the size of components, improve dynamics, and ultimately increase the efficiency. This range has not been yet achieved in power electronics and poses several challenges to be investigated in this project, namely effects of parasitic, simple and power efficient implementation of the control circuitry, matching of power levels to the device needs. In the energy harvesting area, the focus will be on development of matching and power conditioning circuits to extract energy from such sources as piezoceramic generators, photovoltaic, and thermoelectric sources to achieve the highest possible energy yield.

[1] S. Suresh, Y. Lu, and D. Czarkowski, “100 MHz DC-DC Switching Converter with Tracking Control,” Proceedings of the IEEE IECON, Orlando, FL, November 2008.

[2] Y. Lu, S. Suresh, and D. Czarkowski, “Integrated Controller for a 100 MHz DC-DC Switching Converter,” Proceedings of the IEEE APCCAS, P. R. China, November 2008.

[3] Kwok-Kei Ching, “Analysis and design of resonant converters for energy harvesting,” MS Thesis, Polytechnic University, Brooklyn, NY, May 2008.

Analysis of Secondary Networks Having Distributed Generation Systems

Participating Faculty: Dariusz Czarkowski, Francisco De Leon Gomez Maqueo and Zivan Zabar

Distributed Generation (DG) is predicted to play an increasing role in the electric power system of the near future. ‘DG’ means that generators of limited size (from a few kW to a few MW) will be connected to the utility distribution system at customer load levels, at distribution feeder buses, or at substation locations. It is critical that the power system impacts be assessed accurately so that these DG units can be applied in a manner that avoids causing degradation of service, such as power quality, reliability, and control of the utility system.

This project addresses the effects of distributed generators utilizing interposed static converter systems (specifically synchronous-generator/DC-link/utility-line units) on the effect on the network-protectors of transformers during steady state operation, and also on short-circuit fault currents. The system assumed to be balanced and a per-phase analysis was used. One of Consolidated Edison of NYC networks, namely the Sutton network, has been selected as a case study as shown in Fig. 1. This network, one of the smallest in Manhattan, extends from 52^nd to 57^th Street and from 1^st to 5^th Avenue. Using EMTP, the analysis included the complete simulation of the Sutton secondary network with its 12 13.8 kV feeders, and a 9 MW static converter connected at different locations on the primary and on the secondary networks as presented in Fig. 2.

Mitigation of Voltage Disturbances Caused by Nonlinear Electrical Massive Loads

Participating Faculty: Zivan Zabar and Dariusz Czarkowski
Collaborators: Tomasz Sulawa
Project is being conducted by the power group of the ECE department and Polytechnic Institute of NYU.

Power utilities around the world become recently more and more concern about maintaining high quality of power they provide for the customers. The reason for that is both increasing number of nonlinear devices, which cause pollution of the voltage and sensitiveness of other equipment to this pollution. Variation in the voltage level can be seen as annoying blinking of fluorescent lights in our houses, but can also interrupt proper operation of modern industrial machines or even damage some very sensitive appliance. Heavy and nonlinear loads are main sources of the voltage distortion in the electrical power grids. In the example below we can see a heavy induction motor powering a car shredder and causing variation of the voltage on its terminal. This variation transmitted through utility lines may be the reason for improper operation of the machine in the factory or can be seen in the house as a fluctuating light.

Long Island Power Authority and KeySpan Energy sponsor this power research project to investigate and mitigate disturbances in Long Island power network.

Development of a Unit Substation Demand Estimator

Participating Faculty: Dariusz Czarkowski and Zivan Zabar
Collaborator: Yariv Ten-Ami
Sponsor: Consolidated Edison Company New York, NY

Today electric utility companies use a wide range of computerized applications for energy management. These applications have an important role in many aspects in the power system industry. Using real-time measurements and different data analysis methods, these applications are responsible for the creation of reasonable and accurate representation of the network.  These applications are also used for short term and long term load forecasting during significantly degraded operations.

A Unit Substation Demand Estimator (USDE) is needed to estimate missing data from substations in various networks across NYC and Westchester County. As a starting point for this study and the USDE development, Flatbush Brooklyn network has been chosen as the first network to be tested.

This project describes the design and implementation of a USDE. The project presents different methods for estimation of missing data measurements.  Each method is tested in detail to validate the accuracy of the estimated data and an estimation process strategy is suggested.

By using the successive estimation methods and Visual Basic for Application code, a USDE application is developed. The USDE application is then tested and special tuning functions are developed to improve the estimation process and the estimation results.

Mitigation Techniques to Reduce Inrush Currents of Network Transformers

Participating Faculty: Zivan Zabar

Transformer energization at no-load may result in a very high inrush current that is a function of the switching instant of the terminal voltage, which is totally random. In an electric distribution system, a feeder energizes many parallel-connected network transformers. Following maintenance work on the feeder, when its circuit breaker closes, it would need to withstand the combined inrush currents of all those transformers, and that peak current may cause improper operation of protective relays.

One way to reduce that inrush current would be to minimize the residual flux in all the transformer cores. The work includes an investigation, using the EMTP code, of a few possible methods of minimizing the residual flux, and the degree to which each was able to reduce the inrush current. The most applicable method is based on the known principle that demagnetization of an iron core is achieved by repeatedly reversing the voltage at the terminals of the device, while, at the same time, steadily decreasing its magnitude. At utility frequencies, 50 or 60 Hz, the power supply is relatively large. The novel idea here is the use of a very-much-lower-frequency power supply, which leads to a very small power requirement (about 2% of that for a 50 – 60 Hz unit).

The next phase would be the construction and field-testing of a prototype (pending proposal).

Secure Built-In-Self-Test (BIST) Architecture

Participating Faculty: Ramesh Karri

Crypto algorithms are being implemented in hardware to meet high throughput requirements  and widely integrated as crypto accelerators in System-On-Chip (SOC) devices for secure applications ranging from tiny smart cards to high performance routers. In a secure SOC, crypto coprocessors offload intensive arithmetic computations from the host processor. A straightforward way to use BIST to test symmetric block cipher circuits is using an additional Test Pattern Generator (TPG) and Output Response Analyzer (ORA) circuits. In the test mode, the inputs to crypto data path are applied from the TPG instead of the plaintext; the outputs from crypto data path are compressed into ORA as a signature.

In a BIST architecture, the aim of TPG is to provide random inputs to Circuit under Test (CUT). Since exhaustive testing is almost impossible, for example AES data path needs 2¹²⁸ test patterns, the probability distribution for test patterns determines the length of test patterns to insure an acceptable level of fault coverage. LFSR tends to produce test patterns having equal numbers of 0s and 1s on each output test pattern resulting in very long test patterns for some circuits. Weighted random pattern generators bias the distribution of 0s and 1s that makes test patterns more random thereby achieving a higher fault coverage with fewer test patterns. Strong randomness is an inherent feature of crypto algorithms. A block cipher can be considered as an instance of a random permutation over a message block under the control of a key block. In fact, the security of a block cipher can be formalized by pseudorandomness: if there is no way to distinguish the block cipher from an ideal random permutation, then the block cipher can not be attacked.  One or more round operations are non-linear transformations in symmetric block ciphers. For example, in both DES and AES, the non-linear substitution is used. The randomness of several symmetric block cipher algorithms has been evaluated by National Institute of Standards and Technology (NIST).

In BIST technique, the ORA operates as a hash function; it compresses all the test results into a signature. MISR is a simple hash function and widely used as ORA. Collision probability is the most important parameter for a hash function. It is defined as the probability that two different messages have the same hash result. The smaller the collision probability is, the better the hash function. If a result sequence with faulty output vectors can also be compressed into the correct signature, such faults can not be tested. Both the quality of TPG and ORA determines the efficiency of the BIST technique. Block cipher in CBC mode is the one of the most powerful hash function widely used in message authentication code. It is computationally infeasible for such hash functions to find messages x and x’ such that x’ ≠ x and hash (x’) = hash(x). A block cipher can be used either as a TPG with more random output patterns or as an ORA with very low collision probability. Based on this key observation, we develop a BIST technique called Secure BIST to test block cipher modules. In the proposed Secure BIST technique, the output of a crypto core (ciphertext) is fed back to the input of the crypto core (plaintext) in the test mode and the signature is compressed into the output ciphertext register. The proposed Secure BIST technique incurs almost no area overhead by using a crypto module itself as both the TPG and the ORA.

We validated Secure BIST on hardware implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES). The experimental results show that Secure BIST is superior to LFSR-based BIST in terms of area overhead, fault coverage and test sequence length.

[1] Bo Yang and Ramesh Karri, A Secure Built-In Self Test Technique for Crypto Modules in Secure Systems-On-Chip (SOC), submitted to IEEE Transactions on Computer.

Fault Tolerant Nanoscale Systems

Participating Faculty: Ramesh Karri
Collaborators: Alex Orailoglu and Kaijie Wu

New technologies based on nanoscale physical characteristics such as Resonant Tunneling Diodes, Quantum-dot Cellular Automata and molecular electronics have been researched and are being proposed as candidates for next generation device technologies. However, physical limitations at the nanoscale result in highly unreliable fabrication mechanisms which in turn translate into highly unreliable nano devices. Consequently, device failure rates in these emerging nanotechnologies are projected to be in the order of 10^-3-10^-1. Furthermore, the faulty behavior is time varying and hard to model. Overall, fault tolerance is an important system level design objective in these emerging nanotechnologies. In current CMOS based technologies, fault rates are static and in the range 10^-9-10^-7. The typical techniques for addressing reliability in CMOS technologies, namely, extensive testing at manufacturing time, and a limited amount of redundant hardware added into the circuitry for high operation time reliability, cannot be successfully applied in emerging nanotechnologies with much higher and time varying failure rates. Fundamentally, manufacturing processes and hence failure mechanisms are different and the devices per unit area are several orders of magnitude larger (~10⁷ device/cm² in CMOS vs ~10¹² device/cm² in emerging nanotechnologies).

This research investigates design principles for building reliable systems from unreliable nano device technologies of Quantum-dot Cellular Automata (QCA) and Negative Differential Resistance (NDR).

Fault tolerant QCA building block design
Triple Modular Redundancy (TMR) is a straightforward way to provide fault tolerance capability. However, TMR is not a good choice for designing fault tolerant QCA designs since wires, faults in wires, and wire delays dominate in this nanotechnology. We propose TMR using Shifted Operands (TMRSO) as a new approach to designing fault tolerant QCA designs with lower area overhead and better performance than straightforward TMR 0. This new method exploits the self-latching and adiabatic pipelining properties of QCA devices to maximize throughput of a system since more than one calculation can be in the pipeline at a given time. We have validated this concept on a two-bit adder as shown in Figure 1.

Fault Tolerant NDR building block design
Error checking code based information redundancy approach has been regarded as a powerful fault tolerance scheme in communication and storage systems. Preliminary work in this direction has shown that, by exploiting the characteristics of certain Nanotechnology devices, linear block code based information redundancy approach can be applied to carry save based arithmetic subsystems, thus providing a promising vision of further developing a low-overhead unified fault tolerance scheme for Nanotechnology systems 0.

Figure 2 shows an example of fault tolerance carry save addition and the functional flow of the fault detection technique in carry-save addition using linear block coding theory.

Fault tolerant nanotechnology processor design
We propose to investigate a new decentralized architecture that incorporates powerful and flexible fault tolerance strategies in the Nanotechnology environment 0. As a preliminary work, we have developed a fault tolerance strategy with a certain degree of decentralization in computation units that dynamically selects between hardware and time redundancy in response to the time varying fault rates in the system. Figure 3 shows a high-level view of the instruction issue process and the interaction between the voters and the C-units.

[1] T. Wei, K. Wu, R. Karri and A. Orailoglu, Fault Tolerant Quantum Cellular Array (QCA) Design using Triple Modular Redundancy with Shifted Operands, ASP-DAC 2005, to appear

[2] W. Rao, A. Orailoglu and R. Karri, Fault Tolerant Arithmetic with Applications in Nanotechnology based System, International Test Conference, pp. 472-478, October 2004

[3] W. Rao, A. Orailoglu and R. Karri, Fault Tolerant Nanoelectronic Processor Architectures, ASP-DAC 2005, to appear.

Hybrid CMOS/Nano Circuit Design

Participating Faculty: Garrett S. Rose

In recent years many researchers have begun investigating the use of novel nanoelectronic devices in computer systems.  The reason for such interest in nanotechnology stems from the fact that conventional technologies, specifically complementary metal oxide semiconductors (CMOS), are becoming more unreliable and difficult to work with as device feature sizes scale into the nanometer regime. These issues emerge for various reasons, including difficulty in fabricating such small devices, higher sensitivities to parameter variations and characteristics that are increasingly dependent on quantum phenomena.  Novel nanoscale technologies (e.g, quantum cellular automata, single electronics and molecular electronics) offer several potential advantages where issues due to scaling may be adverted or, in some cases, even leveraged as features in new design approaches for digital circuits and architectures.  Of course, conventional CMOS technology has grown strong roots in the microelectronics industry and will not be phased out completely anytime soon.  Thus, the point of this research is not simply an exploration into the use of nanotechnology for digital logic and memory but also how novel nanoelectronic circuits can be integrated with conventional CMOS.  Such hybrid CMOS/Nano systems (illustrated in Figure 1) aim to take advantage of each technology for optimal area utilization, performance, power consumption and design complexity [1, 2].

A Hybrid CMOS/Molecular Memory Design
Many molecular electronic devices fabricated to date have exhibited a property known as hysteresis whereby a device can be made to operate with one of two possible conductivity states.  Since there are two possibilities for conductance, or resistance, the device can be easily used as a memory cell where one conductivity state represents logic 1 and the other logic 0.  Shown below in Figure 2 is a hybrid CMOS/molecular memory design where molecular devices are used to store data and CMOS is used to access the memory.  This memory was designed from a circuit designer’s perspective considering factors such as power consumption, device parameter variations and scalability [3, 4].

On-Chip Characterization of Nanoscale Devices via CMOS Circuitry
An important step in developing hybrid CMOS/molecular circuits is to design CMOS circuitry for the on-chip characterization of molecular electronic devices.  Work has already begun in collaboration with researchers at NIST to design and implement simple circuits (amplifiers, decoders, etc.) that can be fabricated as parts of first generation CMOS/molecular systems.  Current work at Poly has consisted of the design of verification of this test circuitry while collaborators have already begun fabricating molecular electronic devices and circuits.  As this project develops, hybrid CMOS/molecular circuits will not only be designed and verified using CAD tools but will also be realized and tested in the lab, bringing such novel approaches one step closer to reality [5].

[1] M. R. Stan, G. S. Rose, and M. M. Ziegler, “Hybrid CMOS/Molecular Integrated Circuits,” in Moore’s Law: Beyond Planar Silicon CMOS and into the Nano Era, H. Huff, Ed., Springer, in press.

[2] M. R. Stan, G. S. Rose, and M. M. Ziegler, “Hybrid CMOS/molecular Electronic Circuits,” in Proceedings of the International Conference on VLSI Design, Hyderabad, India, Jan. 2006.

[3]  G. S. Rose, Y. Yao, J. M. Tour, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, J. C. Bean, L. R. Harriott, and M. R. Stan, “Designing CMOS/Molecular Memories while Considering Device Parameter Variations,” ACM Journal of Emerging Technologies  in Computing, submitted.

[4]  G. S. Rose, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, M. R. Stan, J. C. Bean, L. R. Harriott, Y. Yao, and J. M. Tour, “Design Approaches for Hybrid CMOS/Molecular Memory Based on Experimental Device Data,” in Proceedings of the ACM Great Lakes Symposium on VLSI, Philadelphia, PA, May 2006, pp. 2-7. (Best student paper.)

[5] N. Gergel-Hackett, G. S. Rose, P. Paliwoda, C. A. Hacker, C. A. Richter, “OnChip Characterization of Molecular Electronic Devices: The Design and Simulation of a Hybrid Circuit Based on Experimental Molecular Electronic Device Results,” in Proceedings of the ACM Great Lakes Symposium on VLSI, 2007, submitted.